1. Field of the Invention
The invention relates generally to methods and apparatus for implementing and controlling cache memory and more particularly relates to methods and apparatus for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments.
2. Description of the Related Art
Cache memories and controllers for cache memories are well known. Devices integrating both memory and control features on a single chip are also known. These include the commercially avaiable 43608 manufactured by NEC and are hereinafter referred to as "Integrated" Cache Units (ICUs).
Prior art ICU devices utilize predetermined algorithms for caching data and instructions i.e., the devices are not programmable. Heretofore, integrating cache memory, a cache controller and programmability features on a single chip has not been achieved due in part to circuit density and data path requirement. In addition to not being programmable, no known ICU architecture has overcome the circuit density and data path requirement problems associated with supporting high speed RISC processing systems, particularly those high speed RISC systems having multiprocessor capabilities.
Further, with reference to multiprocessor and/or multitasking support, the prior art has made use of interlock variables in cache environments for semaphores and other synchronization variables e.g., as protection keys for shared memory areas. In such systems the interlock variables create a special problem, since their access should be synchronized independently of the cache.
A simple prior art solution to this problem is to assign all the interlock variables as non-cacheable. In this case, the interlock variables are not cached and all interlock accesses are directed to the memory. The main disadvantage is the lower performance, and higher bus utilization, caused by the interlock variables accesses to the memory. As the number of interlock accesses grows, the impact on the performance can become severe. Accordingly, a cache unit that allows for the caching of interlock variables is desirable.
Further yet, a programmable ICU with the above interlock variable caching ability would give the user the ability to enable or disable this feature along with providing the inherent flexibility to permit the selection and/or modification of caching algorithms, write policies and other system design criteria.
A single chip ICU architecture with the aforementioned features would also be desirable to minimize space and unit power requirements. Still further, it would be desirable to be able to use such an integrated cache unit to support high speed processing operations in both single and multiprocessor modes, for both RISC and non-RISC environments.